Clock Recovery Unit CR6256-56G
The delay of digital DSP CDR is a thousand times higher than that of analog CDR, and its high delay characteristic makes it difficult to ensure the phase matching between the input signal and the output signal, so that the clock output of the bit error tester can no longer meet the 53Gbaud on the optical port side. 53G PAM4 eye test need to recover the clock signal from the data.
- Description
- Additional information
- Specifications
Description
Clock Recovery Unit CR6256-56G
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Wide range of rates Support 49.7664~56 GBaud/24.8832~28 GBaud |
A wide range of applications IEEE802.3 Ethernet, Fibre Channel and OIF standard specifications for TDECQ indicators; |
Easy to use Built-in touch screen display and control, all functions of clock recovery can be realized without external computer; |
High sensitivity It is very beneficial to the application scenario of silicon photonics under low optical power; |
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Easy to use
Can be used with other sampling oscilloscopes in the industry, with built-in touch screen display and control; |
Flexible configuration Single and multi-mode integration; |
Multiple frequency output
Support 1/2, 1/4@53.125 GBaud; |
Excellent performance
Fast locking, |
Features and Benefits
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LCD screen displays real-time input optical power, monitoring link status at any time |
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Additional information
CR6256 | CR6256 28GBd PAM4 CDR, CR6256-SM 56GBd PAM4 CDR, single mode, CR6256-MM 56GBd PAM4 CDR, single mode+multi mode |
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Clock Recovery Rate Range | 25GBaud~56GBaud |
Signal Format | NRZ/PAM4 |
Optical interface | FC/PC |
Electrical interface | 2.92mm |
Input power range | -14dBm~3dBm |
Receiver sensitivity |
-12dBm@53.125GBaud PAM4;
-14dBm@26.5625GBaud PAM4;
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Wavelength range | 850nm~1650nm |
Optical interface return loss | <-23dB |
Recovery clock divider ratio | 1/2, 1/4@53.125GBaud; 1/1, 1/2@26.5625GBaud; |
Amplitude of Electrical Output | 300mV |
Random Jitter of recovered clock | 290fs |
Impedance | 50Ω |
PLL bandwidth | 20MHz max |